1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a technique of providing a high-speed readable mask ROM.
2. Description of the Related Art
FIG. 6 is a circuit diagram showing a configuration of a contact-type mask ROM as a conventional semiconductor memory device. The contact-type mask ROM has a configuration in which whether or not a drain of a memory cell transistor is connected to a bit line through a contact is associated with “0” and “1” of memory data.
In FIG. 6, the conventional semiconductor memory device is composed of a memory cell array 3, a column decoder 2, a sense amplifier 18, and a charge signal generation circuit 4.
The memory cell array 3 is configured so that memory cells Mij (i=1 to m, J=1 to n) of N-type MOS transistors are arranged in a matrix. Gates of the memory cells Mij are connected respectively to word lines WLi (i=1 to m) commonly in a row direction (memory cells having the same numerical value of i), and sources thereof are grounded. Herein, drains of the memory cells Mij are connected to bit lines BLj (j=1 to n) in the case where memory data is “0”, and are not connected to bit lines BLj (j=1 to n) in the case where the memory data is “1”.
The column decoder 2 is composed of N-type MOS transistors Cj (j=1 to n). All drains of the N-type MOS transistors Cj (j=1 to n) are commonly connected. Gates thereof are connected respectively to column selection signal lines CLj (j=1 to n), and sources thereof are connected respectively to the bit lines BLj (j=1 to n).
The sense amplifier 18 is composed of a P-type MOS transistor 5 for charging (charging circuit), an inverter 8 for determining output data of the memory cells Mij (determination inverter), and an inverter 9 for buffering an output signal of the inverter 8 (buffering inverter). A gate terminal of the P-type MOS transistor 5 receives a charge control signal NPR of the charge signal generation circuit 4. A source terminal thereof is supplied with a supply voltage VDD, and a drain terminal thereof is connected to a common drain of the N-type MOS transistors Cj (j=1 to n). The inverter 8 receives a signal of the common drain of the N-type MOS transistors Cj (j=1 to n), and determines output data of the memory cells Mij. The inverter 9 receives an output signal from the inverter 8, and outputs memory data of the memory cells Mij.
The charge signal generation circuit 4 receives a dock and an address from outside, and outputs the charge control signal NPR to a gate of the P-type MOS transistor 5 for charging.
Next, the operation of reading data of the memory cell M11, as an example, in the semiconductor memory device configured as described above will be described with reference to FIG. 7. FIG. 7 is a timing chart for signals in respective portions of the sense amplifier 18.
First, among the column selection signal lines CLj (j=1 to n), CL1 is changed to a logic “H” level, and the other CL2 to CLn are changed to a logic “L” level, whereby the N-type MOS transistor C1 is turned on among the transistors constituting the column decoder 2, and the other transistors C2 to Cn are turned off. Furthermore, the word line WL1 is changed from the logic “L” level that is a non-selected state to the logic “W” level that is a selected state, and the other word lines WL2 to WLm are retained to be the logic “L” level that is a non-selected state.
Next, the charge control signal NPR is changed from the logic “H” level to the logic “L” level, and the P-type MOS transistor 5 for charging is turned on.
Herein, in the case where the drain of the memory cell M11 is connected to the bit line BL1, the current capability of the memory cell M11 is larger than that of the P-type MOS transistor 5 for charging. Therefore, an input signal SIN (SIN0) of the inverter 8 becomes lower than a switching level VTH of the inverter 8. An output signal SOUT (SOUT0) of the inverter 8 holds the logic “H” level, and an output signal OUT (OUT0) of the inverter 9 holds the logic “L” level.
On the other hand, in the case where the drain of the memory cell M11 is not connected to the bit line BL1, the bit line BL1 is charged by the P-type MOS transistor 5 for charging, and the input signal SIN (SIN1) to the inverter 8 has a voltage higher than the switching level VTH of the inverter 8. Therefore, the output signal SOUT (SOUT1) of the inverter 8 turns to be the logic “L” level, and the output signal OUT (OUT1) of the inverter 9 turns to be the logic “H” level. At this time, a read time tRD is determined by a time during which the P-type MOS transistor 5 for charging charges the bit line BL1.
The above-mentioned conventional semiconductor memory device has the following problem.
In the case where the memory cells Mij are connected to the bit lines BLj, data are determined by setting the level of the input signal SIN (SIN0) to the inverter 8 to be lower than the switching level VTH of the determination inverter 8 under the condition that the P-type MOS transistor 5 for charging and the memory cell Mij are in a ON state. Therefore, the current capability of the P-type MOS transistor 5 for charging is set to be smaller than that of the memory cells Mij.
In recent years, the current capability of the memory cells Mij has decreased along with the miniaturization of a process and the enhanced performance of equipment. Furthermore, the number of the memory cells Mij to be connected to the bit lines BLj is increased to enhance the bit line capacitance. Along with the decrease in current capability of the memory cells Mij, the current capability of the P-type MOS transistor 5 for charging also is decreased, and the capacitance of the bit lines to be charged by the P-type MOS transistor 5 for charging is increased. Therefore, a charge time is prolonged, which results in a prolonged read time tRD.